1. Field of the Invention
The present invention relates to a semiconductor device comprising a plurality of nonvolatile memory cell transistors and a method for manufacturing the same.
2. Description of the Related Art
FIGS. 27A and 27B show cross-sectional views of the conventional nonvolatile semiconductor memory device. FIG. 27A is the cross-sectional view in a channel length direction (bit line direction), while FIG. 27B is the cross-sectional view in a channel width direction (word line direction). FIG. 27B is the cross-sectional view of the nonvolatile semiconductor memory device in a surface orthogonal to the drawing and taken along a line B-B′ in FIG. 27A.
An active area surrounded by an isolation insulating film 92 is provided on the surface of a semiconductor substrate 91. A plurality of impurity diffusion layers 93 are provided in the active area so as to be isolated with each other. A plurality of memory cell transistors M1 to M4, which have a two-layer gate structure constituted of a tunnel insulation film 94, a floating gate electrode 95, an inter-electrode insulation film 96 and a control gate electrode 97, are arranged and provided between adjacent impurity diffusion layers 93.
In addition, a select gate transistor SG, which has a stacked gate electrode structure with a floating gate electrode 95a and a control gate electrode 97a electrically connected, is provided in the both sides (only one side is shown in FIG. 27A) of the plurality of memory cell transistors.
Further, the entire memory cell transistors are covered with an interlayer insulation film 98, a buried layer (plug) 99 to a bit line contact BL (and a source line contact SL) is electrically connected to the impurity diffusion layer 93 provided outside of the select gate transistor SG.
In the constitution of a memory cell array portion in the conventional nonvolatile semiconductor memory device, there is a limit to miniaturize the size of the memory cell transistor. Typically, when the channel length of the memory cell transistor is set to 50 nm or less, an on/off ratio of channel current is lowered due to the so-called short channel effect to cause malfunction of the memory cell transistor.
As a countermeasure for the memory malfunction, Jpn. Pat. Appln. KOKAI Publication No. 2002-289810 proposes the formation of the memory cell array portion on an SOI layer. However, even if such a memory cell array portion is adopted, not all problems of the memory malfunction are solved. That is, the problem of erase malfunction remains unresolved in the prior art.